Clojurians Log v2

Hey team this one more is code-review related to core.async https://github.com/stopachka/ram/blob/55a318bd7cc1948141ff96a8c0cc1bc9b7e3b040/src/ram.clj I want to try to represent circuits + gates with clojure. I thought I could use core.async channels as wires, and build up gates with a nand-gate. Above is an attempt at a beginning for an implementation. I hit some problems pretty quick though: a. My nand-gate implementation is pretty imperative. I wonder if there’s a better way. If you have ideas for a better way to write nand-gate lmk b. My not-gate will fire more than once, because I use mult to copy the input ch, to simulate ~connecting wires. I am not sure if this is the best way to do this. If you have ideas on a better way to write not-gate lmk c. I ended up stuck trying to create the memory-bit. The output bit doesn’t behave as I expect, and. I am realizing it’s pretty hard to introspect and figure out what is going on i. this is making me think that using channels like this may not be the best way to represent circuits. If you have thoughts on introspecting better, or representing circuits, differently, plz lmk a.